NXP Semiconductors P89LPC9321 UM10310 User Manual Page 103
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User manual Rev. 01 — 1 December 2008 103 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
To feed the watchdog, two write instructions must be sequentially executed successfully.
Between the two write instructions, SFR reads are allowed, but writes are not allowed.
The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2
register. An incorrect feed sequence will cause an immediate watchdog reset. The
program sequence to feed the watchdog timer is as follows:
CLR EA ;disable interrupt
MOV WFEED1,#0A5h ;do watchdog feed part 1
MOV WFEED2,#05Ah ;do watchdog feed part 2
SETB EA ;enable interrupt
This sequence assumes that the P89LPC9321 interrupt system is enabled and there is a
possibility of an interrupt request occurring during the feed sequence. If an interrupt was
allowed to be serviced and the service routine contained any SFR writes, it would trigger a
watchdog reset. If it is known that no interrupt could occur during the feed sequence, the
instructions to disable and re-enable interrupts may be removed.
In watchdog mode (WDTE = 1), writing the WDCON register must be IMMEDIATELY
followed by a feed sequence to load the WDL to the 8-bit down counter, and the WDCON
to the shadow register. If writing to the WDCON register is not immediately followed by the
feed sequence, a watchdog reset will occur.
For example: setting WDRUN = 1:
MOV ACC,WDCON ;get WDCON
SETB ACC.2 ;set WD_RUN=1
MOV WDL,#0FFh ;New count to be loaded to 8-bit down counter
CLR EA ;disable interrupt
MOV WDCON,ACC ;write back to WDCON (after the watchdog is enabled, a feed
must occur ; immediately)
MOV WFEED1,#0A5h ;do watchdog feed part 1
MOV WFEED2,#05Ah ;do watchdog feed part 2
SETB EA ;enable interrupt
In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle
(no feed sequence is required to load the control register), but a feed sequence is
required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.
The number of watchdog clocks before timing out is calculated by the following equations:
(1)
where:
PRE is the value of prescaler (PRE2 to PRE0) which can be the range 0 to 7, and;
WDL is the value of watchdog load register which can be the range of 0 to 255.
The minimum number of tclks is:
(2)
The maximum number of tclks is:
tclks 2
5 PRE+()
()WDL 1+()1+=
tclks 2
50+()
()01+()133=+=
- P89LPC9321 User manual 1
- Contact information 2
- 1. Introduction 3
- 1.2 Pin description 5
- 1.3 Functional diagram 8
- 1.4 Block diagram 9
- NXP Semiconductors 10
- 1.6 Memory organization 20
- 2. Clocks 21
- 2.4 Clock output 22
- 3. Interrupts 25
- 4. I/O ports 28
- 4.1 Port configurations 29
- 4.4 Input-only configuration 31
- 4.7 Additional port features 32
- 5. Power monitoring functions 33
- 5.2 Power-on detection 34
- 5.3 Power reduction modes 34
- 6. Reset 37
- 6.1 Reset vector 38
- 7. Timers 0 and 1 39
- 7.1 Mode 0 40
- 7.2 Mode 1 40
- 002aae091 44
- 8.2 Changing RTCS1/RTCS0 45
- 9. Capture/Compare Unit (CCU) 47
- 9.3 Basic timer operation 48
- 9.4 Output compare 50
- 9.5 Input capture 51
- 9.6 PWM operation 52
- 9.7 Alternating output mode 53
- 9.9 HALT 54
- 9.10 PLL operation 55
- 10. UART 59
- 10.4 Mode 3 60
- 10.5 SFR space 60
- 10.8 Framing error 61
- 10.9 Break detect 61
- 10.10 More about UART Mode 0 63
- 002aaa925 64
- 10.14 Break detect 66
- 10.15 Double buffering 66
- C interface 70
- C data register 71
- C slave address register 71
- C control register 72
- C Status register 73
- C operation modes 74
- 002aaa900 85
- 12.1 Configuring the SPI 88
- 12.4 Mode change on SS 89
- 12.5 Write collision 90
- 12.6 Data mode 90
- 13. Analog comparators 94
- 13.3 Comparator input pins 96
- 13.4 Comparator interrupt 96
- 14. Keypad interrupt (KBI) 100
- 15. Watchdog timer (WDT) 101
- 002aae092 102
- 5 PRE+() 103
- 15.3 Watchdog clock source 105
- 16. Additional features 107
- 16.2 Dual Data Pointers 108
- 16.1 Software reset 108
- 17. Data EEPROM 109
- 17.1 Data EEPROM read 110
- 17.2 Data EEPROM write 110
- 17.3 Hardware reset 111
- 17.6 Data EEPROM Row Fill 111
- 18. Flash memory 112
- 18.7 Boot ROM 117
- 18.13 IAP authorization key 122
- 18.14 Flash write enable 122
- 18.16 IAP error status 123
- 18.18 User security bytes 128
- 18.19 Boot Vector register 129
- 18.20 Boot status register 129
- 19. Instruction set 131
- 20. Legal information 134
- 21. Tables 135
- 22. Figures 137
- 23. Contents 138
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