NXP Semiconductors P89LPC9321 UM10310 User Manual download pdf (Page 55)

User manual Rev. 01 — 1 December 2008 55 of 139

NXP Semiconductors

UM10310

P89LPC9321 User manual

still operate as normal even if it has this added functionality enabled. When the PWM unit

is halted, the timer will still run as normal. The HLTRN bit in TCR20 will be set to indicate

that a halt took place. In order to re-activate the PWM, the user must clear the HLTRN bit.

The user can force the PWM unit into halt by writing a logic 1 to HLTRN bit.

9.10 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a

CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module

provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal

frequency is 1 MHz or higher (The PWM resolution is programmable up to 16 bits by

writing to TOR2H:TOR2L). The PLL is fed an input signal of 0.5 MHz to 1 MHz and

generates an output signal of 32 times the input frequency. This signal is used to clock the

timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This

divider is found in the SFR register TCR21. The PLL frequency can be expressed as

follows:

PLL frequency = PCLK / (N+1)

Where: N is the value of PLLDV3:0.

Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to

PCLK

⁄

Setting the PLLEN bit in TCR20 starts the PLL. When PLLEN is set, it will not read back a

one until the PLL is in lock. At this time, the PWM unit is ready to operate and the timer

can be enabled. The following start-up sequence is recommended:

1. Set up the PWM module without starting the timer.

2. Calculate the right division factor so that the PLL receives an input clock signal of

500 kHz - 1 MHz. Write this value to PLLDV.

3. Set PLLEN. Wait until the bit reads one

4. Start the timer by writing a value to bits TMOD21, TMOD20

When the timer runs from the PLL, the timer operates asynchronously to the rest of the

microcontroller. Some restrictions apply:

Table 43. CCU control register 1 (TCR21 - address F9h) bit allocation

Bit 7 6 5 4 3 2 1 0

SymbolTCOU2---PLLDV.3PLLDV.2PLLDV.1PLLDV.0

Reset0xxx0000

Table 44. CCU control register 1 (TCR21 - address F9h) bit description

Bit Symbol Description

0:3 PLLDV.3:0 PLL frequency divider.

4:6 - Reserved.

7 TCOU2 In basic timer mode, writing a logic 1 to TCOU2 will cause the values to be latched immediately and the

value of TCOU2 will always read as logic 0. In PWM mode, writing a logic 1 to TCOU2 will cause the

contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is

pending, TCOU2 will read as logic 1 and will return to logic 0 when the latching takes place. TCOU2 also

controls the latching of the Output Compare registers OCRAx, OCRBx and OCRCx.

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