NXP Semiconductors P89LPC9321 UM10310 User Manual Page 5
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User manual Rev. 01 — 1 December 2008 5 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
1.2 Pin description
Table 1. Pin description
Symbol Pin Type Description
P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the
port configuration selected. Each port pin is configured independently. Refer to
Section 4.1 “
Port configurations” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/ KBI0 3 I/O P0.0 — Port 0 bit 0.
O CMP2 — Comparator 2 output.
I KBI0 — Keyboard input 0.
P0.1/CIN2B/
KBI1
26 I/O P0.1 — Port 0 bit 1.
I CIN2B — Comparator 2 positive input B.
I KBI1 — Keyboard input 1.
P0.2/CIN2A/
KBI2
25 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
P0.3/CIN1B/
KBI3
24 I/O P0.3 — Port 0 bit 3. High current source.
I CIN1B — Comparator 1 positive input B.
I KBI3 — Keyboard input 3.
P0.4/CIN1A/
KBI4
23 I/O P0.4 — Port 0 bit 4. High current source.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
I AD13 — ADC1 channel 3 analog input.
P0.5/CMPREF/
KBI5
22 I/O P0.5 — Port 0 bit 5. High current source.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
P0.6/CMP1/ KBI6 20 I/O P0.6 — Port 0 bit 6. High current source.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P0.7/T1/KBI7 19 I/O P0.7 — Port 0 bit 7. High current source.
I/O T1 — Timer/counter 1 external count input or overflow output.
I KBI7 — Keyboard input 7.
P1.0 to P1.7 I/O, I
[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for
three pins as noted below. During reset Port 1 latches are configured in the input
only mode with the internal pull-up disabled. The operation of the configurable
Port 1 pins as inputs and outputs depends upon the port configuration selected.
Each of the configurable port pins are programmed independently. Refer to
Section 4.1 “
Port configurations” for details. P1.2 to P1.3 are open drain when
used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
- P89LPC9321 User manual 1
- Contact information 2
- 1. Introduction 3
- 1.2 Pin description 5
- 1.3 Functional diagram 8
- 1.4 Block diagram 9
- NXP Semiconductors 10
- 1.6 Memory organization 20
- 2. Clocks 21
- 2.4 Clock output 22
- 3. Interrupts 25
- 4. I/O ports 28
- 4.1 Port configurations 29
- 4.4 Input-only configuration 31
- 4.7 Additional port features 32
- 5. Power monitoring functions 33
- 5.2 Power-on detection 34
- 5.3 Power reduction modes 34
- 6. Reset 37
- 6.1 Reset vector 38
- 7. Timers 0 and 1 39
- 7.1 Mode 0 40
- 7.2 Mode 1 40
- 002aae091 44
- 8.2 Changing RTCS1/RTCS0 45
- 9. Capture/Compare Unit (CCU) 47
- 9.3 Basic timer operation 48
- 9.4 Output compare 50
- 9.5 Input capture 51
- 9.6 PWM operation 52
- 9.7 Alternating output mode 53
- 9.9 HALT 54
- 9.10 PLL operation 55
- 10. UART 59
- 10.4 Mode 3 60
- 10.5 SFR space 60
- 10.8 Framing error 61
- 10.9 Break detect 61
- 10.10 More about UART Mode 0 63
- 002aaa925 64
- 10.14 Break detect 66
- 10.15 Double buffering 66
- C interface 70
- C data register 71
- C slave address register 71
- C control register 72
- C Status register 73
- C operation modes 74
- 002aaa900 85
- 12.1 Configuring the SPI 88
- 12.4 Mode change on SS 89
- 12.5 Write collision 90
- 12.6 Data mode 90
- 13. Analog comparators 94
- 13.3 Comparator input pins 96
- 13.4 Comparator interrupt 96
- 14. Keypad interrupt (KBI) 100
- 15. Watchdog timer (WDT) 101
- 002aae092 102
- 5 PRE+() 103
- 15.3 Watchdog clock source 105
- 16. Additional features 107
- 16.2 Dual Data Pointers 108
- 16.1 Software reset 108
- 17. Data EEPROM 109
- 17.1 Data EEPROM read 110
- 17.2 Data EEPROM write 110
- 17.3 Hardware reset 111
- 17.6 Data EEPROM Row Fill 111
- 18. Flash memory 112
- 18.7 Boot ROM 117
- 18.13 IAP authorization key 122
- 18.14 Flash write enable 122
- 18.16 IAP error status 123
- 18.18 User security bytes 128
- 18.19 Boot Vector register 129
- 18.20 Boot status register 129
- 19. Instruction set 131
- 20. Legal information 134
- 21. Tables 135
- 22. Figures 137
- 23. Contents 138
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