NXP Semiconductors P89LPC9321 UM10310 User Manual download pdf (Page 51)

User manual Rev. 01 — 1 December 2008 51 of 139

NXP Semiconductors

UM10310

P89LPC9321 User manual

In order for a Compare Output Action to occur, the compare values must be within the

counting range of the CCU timer.

When the compare channel is enabled, the I/O pin (which must be configured as an

output) will be connected to an internal latch controlled by the compare logic. The value of

this latch is zero from reset and can be changed by invoking a forced compare. A forced

compare is generated by writing a logic 1 to the Force Compare x Output bit - FCOx bit in

OCCRx. Writing a one to this bit generates a transition on the corresponding I/O pin as set

up by OCMx1/OCMx0 without causing an interrupt. In basic timer operating mode the

FCOx bits always read zero. (Note: This bit has a different function in PWM mode.) When

an output compare pin is enabled and connected to the compare latch, the state of the

compare pin remains unchanged until a compare event or forced compare occurs.

When the user writes to change the output compare value, the values written to OCRH2x

and OCRL2x are transferred to two 8-bit shadow registers. In order to latch the contents

of the shadow registers into the capture compare register, the user must write a logic 1 to

the CCU Timer Compare/Overflow Update bit TCOU2, in the CCU Control Register 1 -

TCR21. The function of this bit depends on whether the timer is running in PWM mode or

in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to

be latched immediately and the value of TCOU2 will always read as zero. In PWM mode,

writing a one to TCOU2 will cause the contents of the shadow registers to be updated on

the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as one and

will return to zero when the latch takes place. TCOU2 also controls the latching of all the

Output Compare registers as well as the Timer Overflow Reload registers - TOR2.

9.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input

capture pins, the contents of the timer is transferred to the corresponding 16-bit input

capture register ICRAH:ICRAL or ICRBH:ICRBL. The capture event is defined by the

Table 39. Capture compare control register (CCRx - address Exh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol ICECx2 ICECx1 ICECx0 ICESx ICNFx FCOx OCMx1 OCMx0

Reset00000000

Table 40. Capture compare control register (CCRx - address Exh) bit description

Bit Symbol Description

0 OCMx0 Output Compare x Mode. See Table 42 “

Output compare pin behavior.”

1OCMx1

2 FCOx Force Compare X Output Bit. When set, invoke a force compare.

3 ICNFx Input Capture x Noise Filter Enable Bit. When logic 1, the capture logic needs to see four consecutive

samples of the same value in order to recognize an edge as a capture event. The inputs are sampled

every two CCLK periods regardless of the speed of the timer.

4 ICESx Input Capture x Edge Select Bit. When logic 0: Negative edge triggers a capture, When logic 1: Positive

edge triggers a capture.

5 ICECx0 Capture Delay Setting Bit 0. See Table 41

for details.

6 ICECx1 Capture Delay Setting Bit 1. See Table 41

for details.

7 ICECx2 Capture Delay Setting Bit 2. See Table 41

for details.

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 138 139

Comments to this Manuals

No comments

NXP Semiconductors P89LPC9321 UM10310 User Manual Page 51

Comments to this Manuals