NXP Semiconductors P89LPC9321 UM10310 User Manual download pdf (Page 38)

User manual Rev. 01 — 1 December 2008 38 of 139

NXP Semiconductors

UM10310

P89LPC9321 User manual

[1] The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

6.1 Reset vector

Following reset, the P89LPC9321 will fetch instructions from either address 0000h or the

Boot address. The Boot address is formed by using the Boot Vector as the high byte of the

address and the low byte of the address = 00h. The Boot address will be used if a UART

Fig 14. Block diagram of reset

RPE (UCFG1.6)

RST pin

WDTE (UCFG1.7)

watchdog timer reset

software reset SRST (AUXR1.3)

power-on detect

UART break detect

EBRR (AUXR1.6)

brownout detect reset

chip reset

002aae129

Table 22. Reset Sources register (RSTSRC - address DFh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol - BOIF BOF POF R_BK R_WD R_SF R_EX

Reset

[1]

x0110000

Table 23. Reset Sources register (RSTSRC - address DFh) bit description

Bit Symbol Description

0 R_EX external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared by software by writing a

logic 0 to the bit or a Power-on reset. If RST

is still asserted after the Power-on reset is over, R_EX will be set.

1 R_SF software reset Flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset

2 R_WD Watchdog Timer reset flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset.(NOTE:

UCFG1.7 must be = 1)

3 R_BK break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1, a system reset will occur.

This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a

logic 0 to the bit or on a Power-on reset.

4 POF Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up

condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a

Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)

5 BOF BOD Reset Flag. When BOD Reset is activated, this bit is set. It will remain set until cleared by software by

writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag

bits are cleared.)

6 BOIF BOD Interrupt Flag. When BOD Interrupt is activated, this bit is set. It will remain set until cleared by software

by writing a logic 0 to the bit.

7 - reserved

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 138 139

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